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sn54abt16601, sn74abt16601 18-bit universal bus transceivers with 3-state outputs scbs210c june 1992 revised january 1997 1 post office box 655303 ? dallas, texas 75265 members of the texas instruments widebus ? family state-of-the-art epic- ii b ? bicmos design significantly reduces power dissipation ubt ? (universal bus transceiver) combines d-type latches and d-type flip-flops for operation in transparent, latched, clocked, or clock-enabled mode latch-up performance exceeds 500 ma per jedec standard jesd-17 typical v olp (output ground bounce) < 0.8 v at v cc = 5 v, t a = 25 c flow-through architecture optimizes pcb layout package options include plastic 300-mil shrink small-outline (dl) and thin shrink small-outline (dgg) packages and 380-mil fine-pitch ceramic flat (wd) package using 25-mil center-to-center spacings description these 18-bit universal bus transceivers combine d-type latches and d-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes. data flow in each direction is controlled by output-enable (oeab and oeba ), latch-enable (leab and leba), and clock (clkab and clkba) inputs. the clock can be controlled by the clock-enable (clkenab and clkenba ) inputs. for a-to-b data flow, the device operates in the transparent mode when leab is high. when leab is low, the a data is latched if clkab is held at a high or low logic level. if leab is low, the a data is stored in the latch/flip-flop on the low-to-high transition of clkab. output enable oeab is active low. when oeab is low, the outputs are active. when oeab is high, the outputs are in the high-impedance state. data flow for b to a is similar to that of a to b, but uses oeba , leba, clkba, and clkenba . to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. the sn54abt16601 is characterized for operation over the full military temperature range of 55 c to 125 c. the sn74abt16601 is characterized for operation from 40 c to 85 c. copyright ? 1997, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. widebus, epic- ii b, and ubt are trademarks of texas instruments incorporated. sn54abt16601 . . . wd package sn74abt16601 . . . dgg or dl package (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 oeab leab a1 gnd a2 a3 v cc a4 a5 a6 gnd a7 a8 a9 a10 a11 a12 gnd a13 a14 a15 v cc a16 a17 gnd a18 oeba leba clkenab clkab b1 gnd b2 b3 v cc b4 b5 b6 gnd b7 b8 b9 b10 b11 b12 gnd b13 b14 b15 v cc b16 b17 gnd b18 clkba clkenba
sn54abt16601, sn74abt16601 18-bit universal bus transceivers with 3-state outputs scbs210c june 1992 revised january 1997 2 post office box 655303 ? dallas, texas 75265 function table 2 inputs output clkenab oeab leab clkab a b x h x x x z x lh xl l x lh xh h h ll xxb 0 3 h ll xxb 0 3 l ll ll l ll hh l ll lxb 0 3 l l l h x b 0 2 a-to-b data flow is shown: b-to-a flow is similar but uses oeba , leba, clkba, and clkenba . 3 output level before the indicated steady-state input conditions were established output level before the indicated steady-state input conditions were established, provided that clkab was low before leab went low
sn54abt16601, sn74abt16601 18-bit universal bus transceivers with 3-state outputs scbs210c june 1992 revised january 1997 3 post office box 655303 ? dallas, texas 75265 logic diagram (positive logic) ce 1d c1 clk ce 1d c1 clk b1 oeab clkenab clkab leab leba clkba clkenba oeba a1 1 56 55 2 28 30 29 27 3 54 to 17 other channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, v cc 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (except i/o ports) (see note 1) 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the high or power-off state, v o 0.5 v to 5.5 v . . . . . . . . . . . . . . . . . . . current into any output in the low state, i o : sn54abt16601 96 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sn74abt16601 128 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0) 18 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, q ja (see note 2): dgg package 81 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dl package 74 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observe d. 2. the package thermal impedance is calculated in accordance with eia/jedec std jesd51.
sn54abt16601, sn74abt16601 18-bit universal bus transceivers with 3-state outputs scbs210c june 1992 revised january 1997 4 post office box 655303 ? dallas, texas 75265 recommended operating conditions (see note 3) sn54abt16601 sn74abt16601 unit min max min max unit v cc supply voltage 4.5 5.5 4.5 5.5 v v ih high-level input voltage 2 2 v v il low-level input voltage 0.8 0.8 v v i input voltage 0 v cc 0 v cc v i oh high-level output current 24 32 ma i ol low-level output current 48 64 ma d t/ d v input transition rise or fall rate outputs enabled 10 10 ns/v t a operating free-air temperature 55 125 40 85 c note 3: unused pins (input or i/o) must be held high or low to prevent them from floating. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions t a = 25 c sn54abt16601 sn74abt16601 unit parameter test conditions min typ 2 max min max min max unit v ik v cc = 4.5 v, i i = 18 ma 1.2 1.2 1.2 v v cc = 4.5 v, i oh = 3 ma 2.5 2.5 2.5 v oh v cc = 5 v, i oh = 3 ma 3 3 3 v v oh v cc =45v i oh = 24 ma 2 2 v v cc = 4 . 5 v i oh = 32 ma 2* 2 v ol v cc =45v i ol = 48 ma 0.55 0.55 v v ol v cc = 4 . 5 v i ol = 64 ma 0.55* 0.55 v v hys 100 mv i i control inputs v cc =55v v i =v cc or gnd 1 1 1 m a i i a or b ports v cc = 5 . 5 v , v i = v cc or gnd 20** 100 20 m a i off v cc = 0, v i or v o 4.5 v 100 100 m a i cex v cc = 5.5 v, v o = 5.5 v outputs high 50 50 50 m a i o 3 v cc = 5.5 v, v o = 2.5 v 50 100 180 50 180 50 180 ma i ozh v cc = 5.5 v, v o = 2.7 v 10 10 10 m a i ozl v cc = 5.5 v, v o = 0.5 v 10 10 10 m a v cc = 5.5 v, outputs high 1.9 3 2 3 i cc a or b ports v cc = 5 . 5 v , i o = 0, outputs low 28 36 35 36 ma v i = v cc or gnd outputs disabled 1.6 3 2 3 d i ? v cc = 5.5 v, one input at 3.4 v, 50 50 m a d i cc ? cc ,, other inputs at v cc or gnd 1.5 ma c i control inputs v i = 2.5 v or 0.5 v 3 pf c io a or b ports v o = 2.5 v or 0.5 v 9 pf * on products compliant to mil-prf-38535, this parameter does not apply. ** this limit applies only to the sn74abt16601. 2 all typical values are at v cc = 5 v. 3 not more than one output should be tested at a time, and the duration of the test should not exceed one second. the parameters i ozh and i ozl include the input leakage current. ? this is the increase in supply current for each input that is at the specified ttl voltage level rather than v cc or gnd.
sn54abt16601, sn74abt16601 18-bit universal bus transceivers with 3-state outputs scbs210c june 1992 revised january 1997 5 post office box 655303 ? dallas, texas 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 1) sn54abt16601 sn74abt16601 unit min max min max unit f clock clock frequency 0 150 0 150 mhz t pulse duration leab or leba high 2.5 2.5 ns t w p u lse d u ration clkab or clkba high or low 3 3 ns a before clkab or b before clkba 4.6 4 t setu p time a before leab or b before leba ??k ???? ?? ?? ?? ? ? ??? ??? ? ????? ???? ?? ? ????? ???? ??k ??? ?? ? ?? ??k?? ????? ??k 2.9 2.5 a after clkab or b after clkba 0.4 0 t h hold time a after leab or b after leba 2.8 2 ns clken after clk 0 0 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, c l = 50 pf (unless otherwise noted) (see figure 1) sn54abt16601 parameter from (input) to (output) v cc = 5 v, t a = 25 c min max unit min typ max f max 150 200 150 mhz t plh aorb bora 1.5 2.5 4.1 1 4.6 ns t phl a or b b or a 1.5 3.4 4.7 1 5.1 ns t plh leab or leba bora 2 3.4 4.7 1 5.6 ns t phl leab or leba b or a 2 3.7 5 1 5.5 ns t plh clkab or clkba bora 1.5 3.2 4.5 1 5.2 ns t phl clkab or clkba b or a 1.5 3.2 4.4 1 5 ns t pzh oeab or oeba bora 2 4 5 1 5.7 ns t pzl oeab or oeba b or a 2 4.2 5.6 1 6 ns t phz oeab or oeba bora 2 4.5 5.8 1 6.8 ns t plz oeab or oeba b or a 1.5 3.4 5.3 1 6.3 ns
sn54abt16601, sn74abt16601 18-bit universal bus transceivers with 3-state outputs scbs210c june 1992 revised january 1997 6 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, c l = 50 pf (unless otherwise noted) (see figure 1) sn74abt16601 parameter from (input) to (output) v cc = 5 v, t a = 25 c min max unit min typ max f max 150 200 150 mhz t plh aorb bora 1.5 2.5 3.6 1.5 4 ns t phl a or b b or a 1.5 3.4 4.7 1.5 4.9 ns t plh leab or leba bora 2 3.4 4.7 2 5 ns t phl leab or leba b or a 2 3.7 5 2 5.2 ns t plh clkab or clkba bora 1.5 3.2 4.5 1.5 4.7 ns t phl clkab or clkba b or a 1.5 3.2 4.4 1.5 4.6 ns t pzh oeab or oeba bora 2 4 5 2 5.5 ns t pzl oeab or oeba b or a 2 4.2 5.6 2 5.8 ns t phz oeab or oeba bora 2 4.5 5.4 2 6.2 ns t plz oeab or oeba b or a 1.5 3.4 4.7 1.5 5.4 ns
sn54abt16601, sn74abt16601 18-bit universal bus transceivers with 3-state outputs scbs210c june 1992 revised january 1997 7 post office box 655303 ? dallas, texas 75265 parameter measurement information 1.5 v t h t su from output under test c l = 50 pf (see note a) load circuit s1 7 v open gnd 500 w 500 w data input timing input 1.5 v 3 v 0 v 1.5 v 1.5 v 3 v 0 v 3 v 0 v 1.5 v t w input voltage waveforms setup and hold times voltage waveforms propagation delay times inverting and noninverting outputs voltage waveforms pulse duration t plh t phl t phl t plh v oh v oh v ol v ol 1.5 v 1.5 v 3 v 0 v 1.5 v 1.5 v input 1.5 v output control output waveform 1 s1 at 7 v (see note b) output waveform 2 s1 at open (see note b) v ol v oh t pzl t pzh t plz t phz 1.5 v 1.5 v 3.5 v 0 v 1.5 v v ol + 0.3 v 1.5 v v oh 0.3 v 0 v 3 v voltage waveforms enable and disable times low- and high-level enabling output output t plh /t phl t plz /t pzl t phz /t pzh open 7 v open test s1 output control notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.5 ns, t f 2.5 ns. d. the outputs are measured one at a time with one transition per measurement. 1.5 v figure 1. load circuit and voltage waveforms
package option addendum www.ti.com 24-apr-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples 5962-9467101qxa active cfp wd 56 1 tbd a42 n / a for pkg type -55 to 125 5962-9467101qx a snj54abt16601w d SN74ABT16601DGGR active tssop dgg 56 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 abt16601 sn74abt16601dl active ssop dl 56 20 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 abt16601 sn74abt16601dlr active ssop dl 56 1000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 abt16601 snj54abt16601wd active cfp wd 56 1 tbd a42 n / a for pkg type -55 to 125 5962-9467101qx a snj54abt16601w d (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
package option addendum www.ti.com 24-apr-2015 addendum-page 2 (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of sn54abt16601, sn74abt16601 : ? catalog: sn74abt16601 ? military: sn54abt16601 note: qualified version definitions: ? catalog - ti's standard catalog product ? military - qml certified for military and defense applications
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant SN74ABT16601DGGR tssop dgg 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 q1 sn74abt16601dlr ssop dl 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 q1 package materials information www.ti.com 14-jul-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) SN74ABT16601DGGR tssop dgg 56 2000 367.0 367.0 45.0 sn74abt16601dlr ssop dl 56 1000 367.0 367.0 55.0 package materials information www.ti.com 14-jul-2012 pack materials-page 2
mechanical data mcfp010b january 1995 revised november 1997 post office box 655303 ? dallas, texas 75265 wd (r-gdfp-f**) ceramic dual flatpack 4040176 / d 10/97 48 leads shown 48 48 25 56 0.610 (18,80) 0.710 (18,03) 0.740 0.640 0.390 (9,91) 0.370 (9,40) 0.870 (22,10) 1.130 (28,70) 1 a 0.120 (3,05) 0.075 (1,91) leads** 24 no. of a min a max (16,26) (15,49) 0.025 (0,635) 0.009 (0,23) 0.004 (0,10) 0.370 (9,40) 0.250 (6,35) 0.370 (9,40) 0.250 (6,35) 0.014 (0,36) 0.008 (0,20) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a ceramic lid using glass frit. d. index point is provided on cap for terminal identification only e. falls within mil std 1835: gdfp1-f48 and jedec mo -146aa gdfp1-f56 and jedec mo -146ab

www.ti.com package outline c typ 8.3 7.9 1.2 max 54x 0.5 56x 0.27 0.17 2x 13.5 (0.15) typ 0 - 8 0.15 0.05 0.25 gage plane 0.75 0.50 a note 3 14.1 13.9 b 6.2 6.0 4222167/a 07/2015 tssop - 1.2 mm max height dgg0056a small outline package notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. reference jedec registration mo-153. 1 56 0.08 c a b 29 28 pin 1 id area seating plane 0.1 c see detail a detail a typical scale 1.200
www.ti.com example board layout (7.5) 0.05 max all around 0.05 min all around 56x (1.5) 56x (0.3) 54x (0.5) (r ) typ 0.05 4222167/a 07/2015 tssop - 1.2 mm max height dgg0056a small outline package symm symm land pattern example scale:6x 1 28 29 56 notes: (continued) 5. publication ipc-7351 may have alternate designs. 6. solder mask tolerances between and around signal pads can vary based on board fabrication site. metal solder mask opening non solder mask defined solder mask details solder mask opening metal under solder mask solder mask defined
www.ti.com example stencil design (7.5) 54x (0.5) 56x (0.3) 56x (1.5) (r ) typ 0.05 4222167/a 07/2015 tssop - 1.2 mm max height dgg0056a small outline package notes: (continued) 7. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 8. board assembly site may have different recommendations for stencil design. symm symm 1 28 29 56 solder paste example based on 0.125 mm thick stencil scale:6x
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